The ever-increasing complexity of integrated circuits, especially logic devices, i.e., integrated circuits that comprise logic circuits, has led to logic devices being designed with a built-in self-test system (BIST) to facilitate testing during manufacture. Automatic test equipment (ATE) is still used to test the logic device, but the automatic test equipment simply controls the BIST and evaluates a test result generated by the BIST.
Some built-in test systems use scan chains to convey stimulus vectors from a stimulus source to various parts of the logic device under test and to convey responses from various parts of the logic device under test to a digital signature generator. The digital signature generator performs data compression on the responses generated by each test to generate a single digital signature that represents all the responses generated by the test. The BIST uploads the digital signature to the ATE as the test result for the logic device under test. The ATE compares the digital signature with an expected signature: a difference between the digital signature and the expected signature indicates that the logic device under test is faulty. The response compression process substantially reduces the data flow from the BIST to the ATE but only allows the ATE to determine whether the logic device under test as a whole has passed or failed the test. The response compression process prevents the ATE from identifying the portion of the logic device under test that has caused the logic device under test as a whole to fail the test. Such information is highly desirable, especially to allow process optimization during production ramp-up but also during on-going production to facilitate process control.
FIG. 1A is a block diagram of an example of a logic device under test 10 being tested by automatic test equipment 12. Logic device 10 comprises logic circuits 14 and an example of a built-in self-test system (BIST) 16. BIST 16 is a pseudo-random BIST or any other deterministic BIST, including any BIST that employs reseeding techniques. Examples of commercially-available BISTs include those sold by Synopsys, Inc., Mountain View, Calif. under the name SoCBIST, and those sold by Mentor Graphics Corp., Wilsonville, Oreg. under the registered trademark TestKompress.
The example of BIST 16 shown is composed of a stimulus generator (SG) 20, a digital signature generator (DSG) 22, scan chains 24 and a BIST controller 26. Stimulus generator 20 has a seed input 21 via which it receives a seed from ATE 12. Digital signature generator 22 has a digital signature output 23 from which it outputs the digital signature it generates to ATE 12 at the end of the testing. Each of the scan chains 24 extends between stimulus generator 20 and digital signature generator 22 and is additionally connected to at least one of the logic circuits 14. BIST controller 26 controls the operation of the remaining elements of BIST 16.
In operation, BIST 16 performs a sequence of tests to test logic device under test 10. During the sequence of tests, ATE 12 provides a seed to the seed input 21 of stimulus generator 20 and stimulus generator 20 generates a sequence of stimulus vectors based the seed. Typically, stimulus generator 20 is a linear feedback shift register (LFSR). Stimulus generator 20 outputs each stimulus vector in the sequence of stimulus vectors to the inputs of scan chains 24. Scan chains 24 apply the stimulus vectors to logic circuits 14. The logic circuits generate respective responses to each stimulus vector. Scan chains 24 capture the responses and shift the responses towards digital signature generator 24. In the example shown, digital signature generator 22 is a multiple input shift register (MISR). In other embodiments, digital signature generator 22 is embodied as a combinatorial network known as an X-Compactor. Digital signature generator 22 generates a digital signal in response to the responses output by all the scan chains over the test sequence. The digital signature represents the response of device under test 10 to the stimulus vectors input during the test sequence. At the end of the test sequence, BIST 16 outputs the digital signature to ATE 12, which compares the digital signature with an expected signature for the test sequence. Any mismatch between the digital signature and the expected signature indicates that device under test 10 is faulty.
FIGS. 1B and 1C are flow charts illustrating the operation of a pseudo-random embodiment and a deterministic embodiment, respectively, of BIST 16 described above with reference to FIG. 1A. Referring first to FIG. 1B, execution begins at block 30. In block 32, stimulus generator 20 is initialized with a seed received from ATE 12. In block 34, a next stimulus vector (SV) is generated. In block 36, the stimulus vector generated in block 34 is applied to logic circuits 14 by scan chains 24. In block 38, the responses generated by logic circuits 14 in response to the stimulus vector are captured by scan chains 24. In block 40, the responses captured by the scan chains are shifted towards the outputs of the scan chains, and, after each shift operation, the responses output from the scan chains are input to digital signature generator 22. In block 42, digital signature generator 22 generates a digital signature from the responses it receives from scan chains 24 during the test sequence. In block 44, a test is performed to determine whether all the tests in the test sequence have been performed. A NO result in block 44 returns execution to block 34. A YES result in block 44 advances execution to block 46, where the digital signature generated by digital signature generator 22 is output to ATE 12 for comparison with an expected signature. A difference between the digital signature output to the ATE in block 46 and the expected signature indicates that logic device under test 10 is faulty. However, such difference gives no indication as to the location of the fault in device under test 10.
The flow chart shown in FIG. 1C is substantially the same as the flow chart just described with reference to FIG. 1B, except that, in block 33, stimulus generator 20 is initialized with a new seed provided by ATE 12 for every test, and a NO result in block 42 returns execution to block 33 instead of to block 34.
In either of the flow charts described above with reference to FIGS. 1B and 1C, the digital signature generated by the test sequence is output to ATE 12 after the entire test sequence has been performed, i.e., all the stimulus vectors have been applied to device under test 10 and all the responses have contributed to the digital signature. The number of test cycles needed to apply all the stimulus vectors and to output all the responses is known in advance. Hence, ATE 12 can be programmed to receive the digital signature generated by digital signature generator 22 after the predetermined number of test cycles has been performed.
While the above-described way of capturing the responses and providing them to the ATE for comparison allows the ATE to operate deterministically, it also results in a loss of diagnostic information. Specifically, outputting the digital signature generated by digital signature generator 22 at the end of the test sequence loses information indicating the exact time at which device under test 10 generated each fault-indicating response. This precludes identifying the test cycle in which the device under test generated the fault-indicating response. Moreover, representing all the responses with a digital signature precludes identifying the scan chain and the cell responsible for the fault-indicating response. As noted above, such diagnostic information is highly important during production ramp and is important during on-going production. Dividing the test sequence executed by BIST 16 into sections known as windows does not remedy this shortcoming without additional testing, which is undesirable.
Conventional BISTs such as those described above do not allow the ATE to react to a fault-indicating response. The ATE has no indication that the device under test has generated a fault-indicating response until the end of the test sequence or the end of the window. Moreover, information regarding the fault-indicating response is lost as the BIST continues to operate after a fault-indicating response has been output to digital signature generator 22.
As noted above, digital signature generator 22 may alternatively be embodied as an X-Compactor. Generating the digital signature using an X-Compactor guarantees that a fault-indicating response output by one of the scan chains will be detected at one of the outputs of the X-compactor even in the presence of unknown states on the outputs of the other scan chains. Unlike in the example of BIST 16 described above with reference to FIG. 1A, in which a multi-input shift register is used as digital signature generator 22, in a BIST in which an X-Compactor is used as digital signature generator 22, comparing the digital signature output by the X-Compactor with an expected signature provides an immediate indication that one of the scan chains 24 has output a fault-indicating response. In other words, an X-Compactor used as digital signature generator 22 does not suffer the latency of an MISR. On the other hand, to communicate the digital signature generated an X-Compactor used as digital signature generator 22 to ATE 12 typically requires more communication channels between logic device under test 10 and ATE 12 than the number of communication channels needed when a MISR is used as digital signature generator 22. Increasing the number of communication channels is generally undesirable. Moreover, since the X-Compactor generates a digital signature from the responses output by scan chains 24, the scan chain responsible for the fault-indicating response cannot be identified.
Accordingly, what is needed is a way to obtain diagnostic information from a logic circuit under test having a built-in self-test system.